Axiro Semiconductor Pvt. Ltd. is a leading fabless semiconductor company based in Bengaluru, India, specializing in high-performance chip design for global 5G/6G, defence, satellite communication, and industrial IoT markets. Backed by the Murugappa Group through CG Power, Axiro leverages advanced design capabilities and strategic global manufacturing partnerships to deliver millions of ICs. With a strong focus on innovation, IP ownership in India, and sustainable growth, Axiro is at the forefront of India’s semiconductor mission.

Job Description

We seek a highly skilled and experienced Custom IC Layout Lead to manage multiple analog/mixed-signal IC layout projects and lead a team of junior layout engineers. In this role, you will drive full-chip layout execution across a variety of applications and process technologies, while providing technical direction, mentorship, and project oversight. You will collaborate closely with circuit designers, verification teams, program management, and packaging engineers to ensure first-pass silicon success in complex technologies.

Responsibilities 

• Execute full custom layout of analog/mixed-signal blocks (e.g., ADCs, DACs, PLLs, LDOs, etc.)
• Lead, mentor, and review the work of a team of junior layout engineers, providing technical guidance and quality oversight
• Plan, prioritize, and manage layout execution across multiple concurrent projects, coordinating schedules and resources to meet tapeout deadlines
• Drive layout strategy and technology qualification across multiple process nodes and technologies (e.g., CMOS, SiGe, BiCMOS, SOI, BCD)
• Collaborate with design engineers to optimize layout for performance, area, and reliability
• Perform layout verification, including DRC, LVS, and parasitic extraction
• Apply layout techniques to mitigate issues such as crosstalk, IR drop, and latch-up
• Provide support for post-layout simulations and tapeout activities
• Maintain design documentation and participate in peer layout reviews
• Interface with packaging and assembly teams to ensure compliance with manufacturing rules
• Work with the design and the foundry team for wafer step plan and wafer matrix

Requirements

• Experience: 12-15 years of hands-on experience in RFIC/MMIC/analog/mixed-signal/custom layout design across multiple process technologies (e.g., CMOS, SiGe, BiCMOS, SOI, BCD), including experience managing multiple concurrent projects and mentoring junior layout engineers.
• Leadership & Project Management:
  • Proven track record managing multiple layout projects simultaneously, from planning through tapeout
  • Experience leading, mentoring, and reviewing the work of junior layout engineers, including technical training and career development
  • Strong cross-functional coordination with design, verification, program management, and foundry teams to align priorities and schedules
• Technical Expertise:
  • Proficient in analog and mixed-signal layout design, including ADCs, DACs, PLLs, DC-DC converters, LDOs, Bandgap references, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers
  • Exposure to RF layout techniques and components such as LNA, MIXER, VCO, RX, and TX is a strong plus
• Process Knowledge: Proven experience working across multiple process technologies, including SiGe, BiCMOS, SOI, and BCD, with the ability to ramp new nodes quickly and guide the team through technology-specific layout considerations
• Layout Fundamentals: Deep understanding of matching, electromigration, latch-up, coupling, cross-talk, IR drop, and parasitic considerations
• Tools Proficiency:
  • Experienced with Cadence and Calibre tools in a Linux environment
  • Scripting skills in SKILL and Perl are desirable
• Design Awareness: Ability to interpret and implement design constraints into high-quality, manufacturable layouts
• Cross-Disciplinary Knowledge: Familiarity with package and assembly rules is a plus
• Soft Skills:
  • Strong problem-solving and debugging skills
  • Effective communication and teamwork
  • Flexible, adaptable, and collaborative working style
  • Proven leadership skills, including mentoring, delegating, and providing performance feedback to junior engineers
  • Strong organizational skills to manage multiple projects and competing priorities